1. Field of the Invention
The invention generally relates to improvements in controlling data signals associated with input/output (“I/O”) cells. More specifically, the invention relates to timing control of transmit data signals and dynamic termination of receive data signals associated with such I/O cells.
2. Discussion of Related Art
In present day electronic circuit design, it is common that a designer integrates a number of predefined components described by entries in a library of a computer aided design tool. Each such standard, predefined circuit is often referred to as a “cell” and the design process is often referred to as “standard cell design.” As used herein, cell should be understood as synonymous with widely accepted terms such as “circuit” regardless of whether the features are designed as part of a standard cell design process or by other processes.
I/O cells are devices used to transmit and receive data between electronic devices. Such an I/O cell may exist as a component internal to an I/O device that is programmably configurable according to specifications of the I/O device. For example, a memory controller may be considered an I/O device that comprises an I/O cell for transmitting, or writing, data to a memory component and for receiving, or reading, data from the memory component in a manner consistent with the specifications of the I/O device. Examples of such memory components include a Reduced Latency Dynamic Random Access Memory (“RLDRAM”). Such I/O cells, however, are not exclusive to memory controllers, but can rather be used with, or in a litany of, other electronic devices exchanging data.
These I/O cells often control the data being transmitted and received in a variety of respects that include timing control and noise reduction. The need for strictly controlling data signals is exacerbated as data signaling speeds between electronic devices increase. Typically, digital circuit or cell designs are operated at frequencies defined by one or more periodic clock signals. High speed or higher data signaling speeds means circuits or cells that operate at higher clock signal frequencies as compared to slower cells. Higher data signaling speeds implies shorter durations between logic levels of the data signals. For example, as durations between logical levels of exchanged signals shorten, noise and/or signal irregularities with respect to the operating clock signals have a greater tendency to corrupt data because there exists a greater likelihood that these data corrupting problems will occur during transitions of the data signal or will cause inadvertent transitions in the data signal.
Signal irregularities can result from complexity of functional logic that generates a signal or can be the result of temperature variations and/or process variations in the functional logic of an I/O device. As used herein, functional logic refers to gates and/or other logic devices used in conjunction with generating and/or transmitting a data signal from an electronic device. Such variations in functional logic may also alter timing of a data signal being generated according to the clock signal. Subsequently, this altered data signal may corrupt data when the functional logic outputs the data signal to another device unaware of the altered timing. For example, duty cycle variations of the data signal with respect to the clock signal can be problematic because data transmitted from one circuit may be registered by a receiving circuit with respect to the rising edge and/or the falling edge of the clock signal common to both circuits. When timing of the data signal is altered, the rising and/or falling edges of the data signal are altered in time. Accordingly, a receiving device unaware of such timing alterations may attempt to register the data without regard to those timing alterations. This problem is exacerbated in RLDRAM devices that register signals according to both rising and falling edges of a clock signal (often referred to as Double Data Rate “DDR” devices, or “DDR”). Thus, if the variations in the data signal are not corrected, communicating devices may experience data corruption.
Noise, another data corrupting culprit, affects data by altering the shape of the signal. One predominate cause of noise, particularly in high speed electronics, is voltage reflection. Voltage reflection typically occurs when two or more interconnecting transmission and reception signal lines are improperly matched in terms of impedance. Thus, a transmitted signal may propagate through the transmission line to the interconnect and reflect all or part of the signal to create voltage disturbances for the presently transmitting data. Voltage reflections are more acute in high speed electronics because even sub-nanosecond voltage disturbances from such reflections can alter the high speed transitions of the data signal. As used herein, impedance refers to any impediment to transmission of a signal, such as resistance, capacitance and/or inductance.
As technology in the art of electronics has progressed, data speeds of electronic devices have increased and should continue to increase at drastic rates. Accordingly, the bounds of timing constraints for data exchanges are continually tested. Since voltage reflections and signal irregularities are problems that affect such high speed data exchanges, there exists a need for improved signal control in I/O cells to substantially reduce voltage reflections and signal duty cycle irregularities.